View CY14E256L-SZ25XCT_2802887.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary 256-kbit (32k x 8) nvsram cy14e256l cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-06968 rev. *c revised november 28, 2006 features ? 25 ns and 45 ns access times ? ?hands-off? automatic store on power down with external 68 f capacitor ? store to quantumtrap ? nonvolatile elements is initiated by software, hardware or autostore ? on power-down ? recall to sram initiated by software or power-up ? infinite read, write and recall cycles ? 15 ma typical i cc at 200 ns cycle time ? 1,000,000 store cycles to quantumtrap ? 100-year data retention to quantumtrap ? single 5v operation + 10% ? commercial temperature ? soic package ? rohs compliance functional description the cypress cy14e256l is a fast static ram with a nonvol- atile element in each memory cell. the embedded nonvolatile elements incorporate quantumtrap technology producing the world?s most reliable nonvolat ile memory. the sram provides infinite read and write cycles, while independent, nonvolatile data resides in the highly reliable quantumtrap cell. data transfers from the sram to the nonvolatile elements (the store operation) takes place automatically at power down. on power-up, data is restored to the sram (the recall operation) from the nonvolatile memory. both the store and recall operations are also available under software control. a hardware store may be initiated with hsb pin. logic block diagram store/ recall control power control software detect static ram array 512 x 512 quantum trap 512 x 512 store recall column i/o column dec row decoder input buffers oe ce we hsb v cc v cap a 13 - a 0 a 0 a 1 a 2 a 3 a 4 a 10 a 5 a 6 a 7 a 8 a 9 a 11 a 12 a 13 a 14 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 [+] feedback [+] feedback
preliminary cy14e256l document #: 001-06968 rev. *c page 2 of 16 pin configurations pin definitions pin name i/o type description a 0 ?a 14 input address inputs used to select one of the 32,768 bytes of the nvsram . dq0-dq7 input/output bidirectional data i/o lines . used as input or output lines depending on operation. we input write enable input, active low . when selected low, enables data on the i/o pins to be written to the address location latched by the falling edge of ce . ce input chip enable input, active low . when low, selects the chip. when high, deselects the chip. oe input output enable, active low . the active low oe input enables the data output buffers during read cycles. deasserting oe high causes the i/o pins to tri-state. v ss ground ground for the device . should be connected to ground of the system. v cc power supply power supply inputs to the device . hsb input/output hardware store busy . when low this output indicates a hardware store is in progress. when pulled low external to the chip it will initiate a nonvolatile store operation. a weak internal pull-up resistor keeps this pin high if not connected. (connection optional) v cap power supply autostore ? capacitor . supplies power to nvsram during power loss to store data from sram to nonvolatile elements. nc no connect no connects . this pin is not connected to the die. v cap a 14 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 dq 0 dq 1 dq 2 v ss v cc hsb we a 13 a 8 a 9 a 11 oe a 10 dq 7 dq 6 dq 5 dq 4 dq 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 23 22 21 20 19 18 17 27 26 25 24 28 32 31 30 29 nc nc ce 32 - lead soic top view (not to scale) [+] feedback [+] feedback
preliminary cy14e256l document #: 001-06968 rev. *c page 3 of 16 device operation the cy14e256l nvsram is made up of two functional components paired in the same physical cell. these are a sram memory cell and a nonvolatile quantumtrap cell. the sram memory cell operates as a standard fast static ram. data in the sram can be transferred to the nonvolatile cell (the store operation), or from the nonvolatile cell to sram (the recall operation). this unique architecture allows all cells to be stored and recalled in parallel. during the store and recall operations sram read and write operations are inhibited. the cy14e256l supports infinite reads and writes just like a typical sram. in addition, it provides infinite recall operations from the nonvolatile cells and up to 1 million store operations. sram read the cy14e256l performs a read cycle whenever ce and oe are low while we and hsb are high. the address specified on pins a 0?14 determines which of the 32,768 data bytes will be accessed. when the read is initiated by an address transition, the outputs will be valid after a delay of t aa (read cycle #1). if the read is initiated by ce or oe , the outputs will be valid at t ace or at t doe , whichever is later (read cycle #2). the data outputs will repeatedly respond to address changes within the t aa access time without the need for transitions on any control input pins, and will remain valid until another address change or until ce or oe is brought high, or we or hsb is brought low. sram write a write cycle is performed whenever ce and we are low and hsb is high. the address inputs must be stable prior to entering the write cycle and must remain stable until either ce or we goes high at the end of the cycle. the data on the common i/o pins i/o 0?7 will be written into the memory if it is valid t sd before the end of a we controlled write or before the end of an ce controlled write. it is recommended that oe be kept high during the entire write cycle to avoid data bus contention on common i/o lines. if oe is left low, internal circuitry will turn off the output buffers t hzwe after we goes low. autostore operation the cy14e256l stores data to nvsram using one of three storage operations. these th ree operations are hardware store, activated by hsb , software store, activated by an address sequence, and autostore, on device power down. autostore operation is a un ique feature of quantumtrap technology and is enabled by default on the cy14e256l. during normal operation, the device will draw current from v cc to charge a capacitor connected to the v cap pin. this stored charge will be used by the chip to perform a single store operation. if the voltage on the v cc pin drops below v switch , the part will automatically disconnect the v cap pin from v cc . a store operation will be initiated with power provided by the v cap capacitor. figure 1 shows the proper connecti on of the storage capacitor (v cap ) for automatic store operatio n. refer to the dc charac- teristics table for the size of v cap . the voltage on the v cap pin is driven to 5v by a charge pump internal to the chip. a pull-up should be placed on we to hold it inactive during power-up. figure 1. autostore ? mode figure 2. system power mode [+] feedback [+] feedback
preliminary cy14e256l document #: 001-06968 rev. *c page 4 of 16 in system power mode ( figure 2 ), both v cc and v cap are connected to the +5v power supply without the 68- f capacitor. in this mode the autostore function of the cy14e256l will operate on the stored system charge as power goes down. the user must, however, guarantee that v cc does not drop below 3.6v during the 10-ms store cycle. if an automatic store on power loss is not required, then v cc can be tied to ground and + 5v applied to v cap ( figure 3 ). this is the autostore inhibit mode, in which the autostore function is disabled. if the cy14e256l is operated in this configuration, references to v cc should be changed to v cap throughout this data sheet. in this mode, store operations may be triggered through software control or the hsb pin. it is not permissible to change between these three options ?on the fly?. to reduce unnecessary nonvolatile stores, autostore and hardware store operations will be ignored unless at least one write operation has taken pl ace since the most recent store or recall cycle. soft ware initiated store cycles are performed regardless of whether a write operation has taken place. the hsb signal can be monitored by the system to detect an autostore cycle is in progress. (in the above figures 1 , 2 and 3 * indicates that if hsb is not used, it should be left unconnected.) hardware store (hsb ) operation the cy14e256l provides the hsb pin for controlling and acknowledging the store operations. the hsb pin can be used to request a hardware store cycle. when the hsb pin is driven low, the cy14e256l will conditionally initiate a store operation after t delay . an actual store cycle will only begin if a write to the sram took place since the last store or recall cycle. the hsb pin also acts as an open-drain driver that is internally driven low to indicate a busy condition while the store (initiated by any means) is in progress. sram read and write operations that are in progress when hsb is driven low by any means are given time to complete before the store operation is initiated. after hsb goes low, the cy14e256l will co ntinue sram operations for t delay . during t delay , multiple sram read operations may take place. if a write is in progress when hsb is pulled low it will be allowed a time, t delay , to complete. however, any sram write cycles requested after hsb goes low will be inhibited until hsb returns high. the hsb pin can be used to synchronize multiple cy14e256l while using a single larger capacitor. to operate in this mode the hsb pin should be connected together to the hsb pins from the other cy14e256l. an external pull-up resistor to +5v is required since hsb acts as an open-drain pull-down. the v cap pins from the other cy14e256l parts can be tied together and share a single capacitor. the capacitor size must be scaled by the number of devices connected to it. when any one of the cy14e256l detects a power loss and asserts hsb , the common hsb pin will cause all parts to request a store cycle (a store will take place in those cy14e256l that have been written since the last nonvolatile cycle). during any store operation, regardless of how it was initiated, the cy14e256l will continue to drive the hsb pin low, releasing it only when the store is complete. upon completion of the store operation the cy14e256l will remain disabled until the hsb pin returns high. if hsb is not used, it should be left unconnected. hardware recall (power-up) during power-up, or after any low-power condition (v cc < v switch ), an internal recall request will be latched. when v cc once again exceeds the sense voltage of v switch , a recall cycle will autom atically be initia ted and will take t hrecall to complete. if the cy14e256l is in a write state at the end of power-up recall, the sram data will be corrupted. to help avoid this situation, a 10-kohm resistor should be connected either between we and system v cc or between ce and system v cc . software store data can be transferred from the sram to the nonvolatile memory by a software address sequence. the cy14e256l software store cycle is initia ted by execut ing sequential ce -controlled read cycles from six specific address locations in exact order. during the store cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. once a store cycle is initiated, further i nput and output are disa bled until the cycle is completed. because a sequence of reads from specific addresses is used for store initiation, it is important that no other read or write accesses intervene in the sequence, or the sequence will be aborted and no store or recall will take place. to initiate the software store cycle, the following read sequence must be performed: 1. read address 0x0e38, valid read 2. read address 0x31c7, valid read 3. read address 0x03e0, valid read 4. read address 0x3c1f, valid read 5. read address 0x303f, valid read 6. read address 0x0fc0, initiate store cycle figure 3. autostore inhibit mode [+] feedback [+] feedback
preliminary cy14e256l document #: 001-06968 rev. *c page 5 of 16 the software sequence may be clocked with ce -controlled reads or oe -controlled reads. once the sixth address in the sequence has been entered, the store cycle will commence and the chip will be dis abled. it is important that read cycles and not write cycl es be used in the sequence, although it is not necessary that oe be low for the sequence to be valid. after the t store cycle time has been fulfilled, the sram will again be activated for read and write operation. software recall data can be transferred from the nonvolatile memory to the sram by a software address sequence. a software recall cycle is initiated with a sequence of read operations in a manner similar to the software store initiation. to initiate the recall cycle, the following sequence of ce -controlled read operations must be performed: 1. read address 0x0e38, valid read 2. read address 0x31c7, valid read 3. read address 0x03e0, valid read 4. read address 0x3c1f, valid read 5. read address 0x303f, valid read 6. read address 0x0c63, initiate recall cycle internally, recall is a two-step procedure. first, the sram data is cleared, and second, the nonvolatile information is transferred into the sram cells. after the t recall cycle time the sram will once again be ready for read and write operations. the recall operation in no way alters the data in the nonvolatile elements. data protection the cy14e256l protects data from corruption during low-voltage conditions by inhibiting all externally initiated store and write operations. the low voltage condition is detected when v cc < v switch . if the cy14e256l is in a write mode (both ce and we low) at power-up, after a recall, or after a store, the write will be inhibited until a negative transition on ce or we is detected. this protects against inadvertent writes during power-up or brown-out conditions. noise considerations the cy14e256l is a high-speed memory and so must have a high-frequency bypass capacitor of approximately 0.1 f connected between v cc and v ss , using leads and traces that are as short as possible. as with all high-speed cmos ics, careful routing of power, ground, and signals will reduce circuit noise. low average active power cmos technology provides the cy14e256l the benefit of drawing significantly less curren t when it is cycled at times longer than 50 ns. figure 4 shows the relationship between i cc and read/write cycle ti me. worst-case current consumption is shown for both cmos and ttl input levels (commercial temperature range, vcc = 5.5v, 100% duty cycle on chip enable).only standby current is drawn when the chip is disabled. the overall average current drawn by the cy14e256l depends on the following items: 1. the duty cycle of chip enable. 2. the overall cycle rate for accesses. 3. the ratio of reads to writes. 4. cmos vs. ttl input levels. 5. the operating temperature. 6. the v cc level. 7. i/o loading. preventing stores the store function can be disabled on the fly by holding hsb high with a driver capable of sourcing 30 ma at a v oh of at least 2.2v, as it will have to overpower the internal pull-down device that drives hsb low for 20 s at the onset of a store. when the cy14e256l is connec ted for autostore operation (system v cc connected to v cc and a 68- f capacitor on v cap ) and v cc crosses v switch on the way down, the cy14e256l will attempt to pull hsb low; if hsb doesn?t actually get below v il ,the part will stop trying to pull hsb low and abort the store attempt. figure 4. current vs. cycle time (read) figure 5. current vs. cycle time (write) table 1. hardware mode selection ce we hsb a13?a0 mode i/o power h x h x not selected output high-z standby l h h x read sram output data active l l h x write sram input data active x x l x nonvolatile store output high-z i cc2 [+] feedback [+] feedback
preliminary cy14e256l document #: 001-06968 rev. *c page 6 of 16 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ?65 c to +150 c ambient temperature with power applied............................................. ?55 c to +125 c supply voltage on v cc relative to gnd.......... ?0.5v to 7.0v voltage applied to outputs in high-z state .......................................?0.5v to v cc + 0.5v input voltage ............................................ ?0.5v to vcc+0.5v transient voltage (<20 ns) on any pin to ground potential...................?2.0v to v cc + 2.0v package power dissipation capability (t a = 25c) ................................................... 1.0w surface mount lead soldering temperature (3 seconds) .......................................... +260 c output short circuit current [1] .................................... 15 ma static discharge voltage......... ........... ............ .......... > 2001v (per mil-std-883, method 3015) latch-up current.................................................... > 200 ma operating range range ambient temperature v cc commercial 0 c to +70 c 4.5v to 5.5v dc electrical characteristics over the operating range (v cc = 4.5v to 5.5v) [2] parameter description test conditions min. max. unit i cc1 average v cc current t rc = 25 ns t rc = 45 ns dependent on output loading and cycle rate. values obtained without output loads. i out = 0ma. commercial 97 70 ma ma ma i cc2 average v cc current during store all inputs don?t care, v cc = max. average current for duration t store 3ma i cc3 average v cc current at t avav = 200 ns, 5v, 25c typical we > (v cc ? 0.2). all other inputs cycling. dependent on output loading and cycle rate. values obtained without output loads. 15 ma i cc4 average v cap current during autostore cycle all inputs don?t care, v cc = max. average current for duration t store 2ma i sb v cc standby current ce > (v cc ? 0.2). all others v in < 0.2v or > (v cc ? 0.2v). standby current level after n onvolatile cycle is complete. inputs are static. f = 0mhz. 1.5 ma i ix input leakage current v cc = max., v ss < v in < v cc -1 +1 a i oz off-state output leakage current v cc = max., v ss < v in < v cc , ce or oe > v ih -5 +5 a v ih input high voltage 2.2 v cc + 0.5 v v il input low voltage v ss ? 0.5 0.8 v v oh output high voltage i out = ?2 ma 2.4 v v ol output low voltage i out = 4 ma 0.4 v capacitance [3] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 0 to 3.0v 5pf c out output capacitance 7 pf notes: 1. outputs shorted for no more than one second. no more than one output shorted at a time. 2. typical conditions for the active current shown on the front page of the data sheet are average values at 25c (room temperat ure), and v cc = 5v. not 100% tested. 3. these parameters are guaranteed but not tested. [+] feedback [+] feedback
preliminary cy14e256l document #: 001-06968 rev. *c page 7 of 16 thermal resistance [3] parameter description tes t conditions 32-soic unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia / jesd51. tbd c/w jc thermal resistance (junction to case) tbd c/w ac test loads ac test conditions 5.0v output 30 pf r1 480 ? r2 255 ? input pulse levels .................................................. 0 v to 3 v input rise and fall times (10% - 90%)........................ < 5 ns input and output timing referenc e levels ......... .......... 1.5 v [+] feedback [+] feedback
preliminary cy14e256l document #: 001-06968 rev. *c page 8 of 16 ac switching characteristics parameter description 25ns part 45ns part unit min. max. min. max. cypress parameter alt. parameter sram read cycle t ace t acs chip enable access time 25 45 ns t rc [4] t rc read cycle time 25 45 ns t aa [5] t aa address access time 25 45 ns t doe t oe output enable to data valid 10 20 ns t oha [5] t oh output hold after address change 5 5 ns t lzce [6] t lz chip enable to output active 5 5 ns t hzce [6] t hz chip disable to output inactive 10 15 ns t lzoe [6] t olz output enable to output active 0 0 ns t hzoe [6] t ohz output disable to output inactive 10 15 ns t pu [ 3] t pa chip enable to power active 0 0 ns t pd [3] t ps chip disable to power standby 25 45 ns sram write cycle t wc t wc write cycle time 25 45 ns t pwe t wp write pulse width 20 30 ns t sce t cw chip enable to end of write 20 30 ns t sd t dw data set-up to end of write 10 15 ns t hd t dh data hold after end of write 0 0 ns t aw t aw address set-up to end of write 20 30 ns t sa t as address set-up to start of write 0 0 ns t ha t wr address hold after end of write 0 0 ns t hzwe [6,7] t wz write enable to output disable 10 14 ns t lzwe [6] t ow output active after end of write 5 5 ns autostore/power-up recall parameter description cy14e256l unit min. max. t hrecall [8] power-up recall duration 550 s t store [9] store cycle duration 10 ms v switch low voltage trigger level 4.0 4.5 v t vccrise v cc rise time 150 s notes: 4. we must be high during sram read cycles. 5. device is continuously selected with ce and oe both low. 6. measured 200mv from steady state output voltage. 7. if we is low when ce goes low, the outputs remain in the high-impedance state. 8. t hrecall starts from the time v cc rises above v switch . 9. if an sram write has not taken place since the last non-volatile cycle, no store will take place. [+] feedback [+] feedback
preliminary cy14e256l document #: 001-06968 rev. *c page 9 of 16 software controlled store/recall cycle [10,11] parameter description 25ns part 45ns part unit min. max. min. max. t rc store/recall initiation cycle time 25 45 ns t as address set-up time 0 0 ns t cw clock pulse width 20 30 ns t glax address hold time 20 20 ns t recall recall duration 20 20 s hardware store cycle parameter description cy14e256l unit min max t store [6] store cycle duration 10 ms t delay [12] time allowed to complete sram cycle 1 s t restore [13] hardware store high to inhibit off 700 ns t hlhx hardware store pulse width 15 ns t hlbl hardware store low to store busy 300 ns switching waveforms figure 6. sram read cycle #1: address controlled [4, 5, 14] notes: 10. the software sequence is clocked with ce controlled reads. 11. the six consecutive addresses must be read in the order listed in the mode selection table. we must be high during a ll six consecutive cycles. 12. read and write cycles in progress before hsb are given this amount of time to complete. 13. t restore is only applicable after t store is complete. 14. hsb must remain high during read and write cycles. t rc t aa t oh address dq (data out) data valid [+] feedback [+] feedback
preliminary cy14e256l document #: 001-06968 rev. *c page 10 of 16 figure 7. sram read cycle #2: ce controlled [4,14] figure 8. sram write cycle #1: we controlled [14,15] note: 15. ce or we must be > v ih during address transitions. switching waveforms (continued) address t rc ce t ace t lzce t pd t hzce oe t doe t lzoe t hzoe data valid active standby t pu dq (data out) icc t wc t sce t ha t aw t sa t pwe t sd t hd t hzwe t lzwe address ce we data in data out data valid high impedance previous data [+] feedback [+] feedback
preliminary cy14e256l document #: 001-06968 rev. *c page 11 of 16 figure 9. sram write cycle #2: ce controlled switching waveforms (continued) t wc address t sa t sce t ha t aw t pwe t sd t hd ce we data in data out high impedance data valid [+] feedback [+] feedback
preliminary cy14e256l document #: 001-06968 rev. *c page 12 of 16 figure 10. autostore/power-up recall switching waveforms (continued) v cc v switch t restore autostore power-up recall v reset t store t delay t vsbl hsb dq (data out) power up recall brown out no stroke (no sram writes) no recall (v cc did not go below v reset ) brown out autostore no recall (v cc did not go below v reset ) tm brown out autostore tm recall when v cc returns above vswitch [+] feedback [+] feedback
preliminary cy14e256l document #: 001-06968 rev. *c page 13 of 16 figure 11. ce -controlled software store/recall cycle [11] figure 12. hardware store cycle switching waveforms (continued) t rc t rc t sa t sce t glax t store / t recall data valid data valid address # 1 address # 6 high impedance address ce oe dq (data) a a a a a a a a a a a a a a t hlhx t store t hlbl t delay data valid data valid high impedance high impedance hsb (in) dq (data out) hsb (out) a a a a a a [+] feedback [+] feedback
preliminary cy14e256l document #: 001-06968 rev. *c page 14 of 16 option: t - tape & reel blank - std. speed: 25 - 25 ns 45 - 45 ns package: sz - 32 soic data bus: l - x8 density: 256 - 256 kb voltage: cypress part numbering nomenclature cy 14 e 256 l- sz 25 x c t e - 5.0v nvsram 14 - autostore + software store + hardware store temperature: c - commercial (0 to 70c) pb-free [+] feedback [+] feedback
preliminary cy14e256l document #: 001-06968 rev. *c page 15 of 16 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. autostore and quantumtrap are registered trademar ks of simtek corporation.all produc ts and company names mentioned in this document are the trademarks of their respective holders. ordering information speed (ns) ordering code package diagram package type operating range 25 CY14E256L-SZ25XCT 51-85127 32-pin soic (pb-free) commercial 45 cy14e256l-sz45xct 51-85127 32-pin soic (pb-free) commercial package diagrams pin1id seating plane 1 16 17 32 dimensions in inches[mm] min. max. 0.292[7.416] 0.299[7.594] 0.405[10.287] 0.419[10.642] 0.050[1.270] typ. 0.090[2.286] 0.100[2.540] 0.004[0.101] 0.0100[0.254] 0.006[0.152] 0.012[0.304] 0.021[0.533] 0.041[1.041] 0.026[0.660] 0.032[0.812] 0.004[0.101] reference jedec mo-119 part # s32.3 standard pkg. sz32.3 lead free pkg. 0.014[0.355] 0.020[0.508] 0.810[20.574] 0.822[20.878] 32-pin (300-mil) soic (51-85127) 51-85127-*a [+] feedback [+] feedback
preliminary cy14e256l document #: 001-06968 rev. *c page 16 of 16 document history page document title: cy14e256l 2 56-kbit (32k x 8) nvsram document number: 001-06968 rev. ecn no. issue date orig. of change description of change ** 427789 see ecn tup new data sheet *a 437321 see ecn tup show data sheet on external web *b 472053 see ecn tup updated part numbering nomenclature and ordering information *c 503290 see ecn pci changed from ?advance? to ?preliminary? changed the term ?unlimited? to ?infinite? changed i cc3 value from 10ma to 15ma removed industrial grade mention removed 35ns speed bin removed icc1 values from the dc table for 35 ns industrial grade corrected v il min. spec from (v cc - 0.5) to (v ss - 0.5) removed all references pertaining to oe controlled ?software store and recall? operation changed the address locations of the software store/recall command updated ?part nomenclature table? and ?ordering informationtable? [+] feedback [+] feedback

▲Up To Search▲

Price & Availability of CY14E256L-SZ25XCT

	To Download CY14E256L-SZ25XCT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .